Field of the Invention
The present invention relates to an integrated CMOS circuit arrangement, and method of manufacturing same, having a first MOS transistor formed at a surface of an associated substrate as well as a second MOS transistor which is complementary to the first arranged at the floor of a trench of the substrate.
In CMOS circuits, it must be assured a given increasing integration density a that the n-channel MOS transistors and the p-channel MOS transistors of logical gates are insulated from one another. In particular, the latch-up effect, or a through-connection of a parasitic thyristor between a first and a second supply voltage, must be prevented. To that end, the n-channel or, p-channel MOS transistors, which are potentially arranged in correspondingly doped wells, are surrounded by insulation regions. Additional well or substrate contactings, for example in the form of guard rings, can be provided as a measure against latch-up effects.
It has been proposed a for increasing the packing density a to respectively combine the n-channel MOS transistors and a p-channel MOS transistors in groups in CMOS circuits (see, for example, S. Saito et al., xe2x80x9cA 1-Mbit CMOS DRAM with Fast Page Mode and Static Column Modexe2x80x9d, IEEE J. Sol.-State Circ., Vol. SC-20, page 903, 1985). As a result thereof, the necessary minimum spacing between a n-doped well and n-doped source/drain regions must be adhered to a not between the individual MOS transistors a but only between the corresponding groups. The space requirement per transistor is thereby reduced.
It also the been proposed a see, for example, A. G. Lewis et al., xe2x80x9cPolysilicon TFT Circuit and Performancexe2x80x9d, IEEE J. Sol.-State Circ., Vol. 27, page 1833, 1992), to construct CMOS circuits on the basis of thin-film transistors. The substrates of the n-channel MOS transistors and of the p-channel MOS transistors are thereby implemented separate from one another. Given this structure, an adequate distance for the insulation of the entire arrangement must be adhered to between the source/drain regions of the n-channel MOS transistors and the p-channel source/drain region of the MOS transistors.
Finally, it has been proposed (see IBM TDB, Vol. 27, No. 12, May 1985, pages 6968 through 6970) to apply an insulating layer for the manufacture of a CMOS circuit on a silicon substrate. A polysilicon layer is grown at the surface of the insulating layer and is locally converted into a monocrystalline layer by lateral epitaxy. The n-channel MOS transistors are formed in the silicon substrate. P-channel MOS transistors are formed in the layer that has been grown. The transistors are respectively insulated by insulation regions surrounding them. In the finished arrangement, the n-channel MOS transistors and the p-channel MOS transistors are completely insulated from one another by the insulating layer and the insulation regions. Fundamentally, latch-up cannot not occur because of the insulating layer. The surface requirement of this CMOS circuit, however, is relatively great due to the insulation regions surrounding the transistors.
The present invention is therefore, directed to the development of an integrated CMOS circuit arrangement, and method which exhibits enhanced packing density.
In the integrated CMOS circuit arrangement of the present invention at least one trench is provided in a principal surface of a semiconductor substrate. A first MOS transistor is arranged at the principal surface and a second MOS transistor is arranged at the floor of the trench. The second MOS transistor is complementary to the first MOS transistor. The first MOS transistor and the second MOS transistor are thereby arranged such that a current flux through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the first MOS transistor and the second MOS transistor. The insulation between the source/drain regions of the first MOS transistor and the source/drain regions of the second MOS transistor in this circuit arrangement is assured by the sidewall of the trench. No lateral space requirement parallel to the principal surface is therefore needed for the insulation between the first MOS transistor and the second MOS transistor. The first MOS transistor and the second MOS transistor can adjoin one another in the projection onto the principal surface. In this way, an enhanced packing density is also achieved in the invention CMOS circuit arrangements.
For improving the latch-up strength, it is advantageous to provide an insulating layer in the semiconductor substrate under the first MOS transistor and above the second MOS transistor. This means that the distance of the insulating layer from the principal surface is less than the depth of the trench. The insulating layer is, thus, interrupted by the trench. The insulating layer can be formed with a highly doped layer that is doped with a conductivity type opposite that of the source/drain regions of the first MOS transistor. Alternatively, the insulating layer can be provided of a dielectric material, for example of SiO2 or Si3N4.
A line is preferably provided that proceeds transversely relative to the trench. This line contains a first gate electrode for the first MOS transistor and a second gate electrode for the second MOS transistor. In this way, an electrical connection is formed between the first gate electrode and the second gate electrode without having to require the manufacture of an additional, aligned connection between the first gate electrode and the second gate electrode.
For contacting the source/drain regions of the second MOS transistor, which is arranged at the floor of the trench, it is advantageous to provide a doped, buried layer in the semiconductor substrate under the second MOS transistor. A vertical sub-region of the source/drain region of the second MOS transistor to be contacted then extends down to the buried layer. This vertical sub-region can be manufactured by ion implantation. The buried layer is connected to the respectively required potentials via one or more contacts. As a result there the corresponding source/drain regions are connectable to the respective potentials.
For manufacturing the CMOS circuit arrangement, a region doped with a first conductivity type is preferably formed in the semiconductor substrates wherein this region adjoins a principal surface. A trench is formed whose depth is greater than the depth of the region doped with the first conductivity type. A gate dielectric is formed that at least covers the floor of the trench and the principal surface. A conductive layer is deposited that fills up the trench. Upon employment of a mask that defines a first gate electrode for the first MOS transistor and a second gate electrode for the second MOS transistor, the conductive layer is etched through in the region of the principal surface in a first etching step. As such the floor of the trench remains covered by the conductive layer. The first gate electrode for the first MOS transistor is thereby formed. Subsequently, source/drain regions are formed for the first MOS transistor. The floor of the trench is thereby covered by the conductive layer, which acts as mask. Subsequently, the conductive layer is also etched through at the floor of the trench in a second etching step. Wherein the second gate electrode is formed. For forming source/drain regions for the second MOS transistor, a diffusion source is generated at the uncovered floor of the trench. The source/drain regions of the second MOS transistor are formed by drive-out.
The diffusion source preferably is formed by applying and flowing a doped silicate glass layer. In this case, the diffusion source arises self-aligned only at the floor of the trench.
A line that proceeds transversely over both the first MOS transistor and the second MOS transistor and that contains both the first gate electrode and the second gate electrode preferably is formed from the conductive layer. As a result, the first gate electrode and the second gate electrode are electrically connected to one another in self-aligning fashion. The connection between the first gate electrode and the second gate electrode is required for logical gates.
It is advantageous for forming a logical gate to arrange the first MOS transistor and the second MOS transistor such that the source/drain regions of the first MOS transistor and of the second MOS transistor, which must be connected electrically to one another in the gate, are arranged next to one another in the projection onto the principal surface. For connecting these source/drain regions, a via hole is opened that overlaps the two source/drain regions to be connected. The source/drain regions are connected to one another by a contact that fills the via hole.
For improving the latch-up strength, it lies within the scope of the present invention to employ an SOI substrate as the semiconductor substrate, this, including a silicon wafer, an insulating layer arranged on the silicon wafer and a monocrystalline silicon layer arranged on the insulating layer. In this case, the trench is formed to such a depth that it extends through the monocrystalline silicon layer and the insulating layer into the silicon wafer. The insulating layer in this arrangement prevents a latch-up between the first MOS transistor and the second MOS transistor.
It also lies within the scope of the present invention to provide more than one trench. Further, the cross section of the trench or trenches can be selected stripe-shaped, so that a plurality of MOS transistors are respectively arranged at the floor of the trench and on the principal surface between neighboring trenches. The configuration of the CMOS circuit in this case occurs via the arrangement of the MOS transistors as well as via the structuring of the conductive layer for forming the gate electrodes. It further lies within the scope of the present invention to provide MOS transistors that neighbor one another at the floor of the trench a or at the principal surface a and that are to be connected in series with a common source/drain region via which they are interconnected in series. Both different gate configurations as well as transfer gate circuits or logic circuits can be realized in the CMOS circuit arrangement.
Additional features and advantages of the present invention are described in, and will be apparent from, the Detailed Description of the Preferred Embodiments and the Drawings.